1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) cell, as well as methods for operating and fabricating a DRAM cell. More specifically, the present invention relates to a vertical one-transistor floating-body DRAM cell formed using a process compatible with a bulk CMOS process, wherein charge is stored inside an electrically isolated body region adjacent to the transistor channel region.
2. Related Art
Conventional one-transistor, one-capacitor (1T/1C) DRAM cells require a complex process for fabrication. Moreover, significant area is required to form the capacitor needed for storage of signal charge. Recently, one-transistor, floating-body (1T/FB) DRAM cells using partially-depleted silicon-on-insulator (PD-SOI) processes have been proposed, in which a signal charge is stored inside a floating body region, which modulates the threshold voltage (VT) of the transistor. As a result, the separate capacitor of a 1T/FB DRAM cell can be eliminated, thereby resulting in reduced cell area and higher density. Periodic refresh operations are still required for these 1T/FB DRAM cells to counteract the loss of stored charge through junction leakage, gate tunneling leakage and access-induced hot-carrier injections (HCI).
FIG. 1 is a cross-sectional view of a conventional 1T/FB DRAM cell 100 fabricated using a PD-SOI process. DRAM cell 100 includes silicon substrate 101, buried oxide layer 102, oxide regions 103-104, N++ type source and drain regions 105-106, N+ type source and drain regions 107-108, P type floating body region 109, gate oxide 110, gate electrode 111 and sidewall spacers 112-113. Floating body 109 is isolated by gate oxide 110, buried oxide layer 102 and the source and drain depletion regions 107xe2x80x2 and 108xe2x80x2. The partially-depleted floating body 109 is used for storing signal charges that modulate the threshold voltage (VT) of DRAM transistor 100 differently when storing different amount of charge. The source node 105 is typically grounded.
A logic xe2x80x9c1xe2x80x9d data bit is written into DRAM cell 100 by biasing drain node 106 at a high voltage and gate node 111 at a mid-level voltage to induce hot-carrier injection (HCI), whereby hot-holes are injected into floating body node 109, thereby raising the voltage level of floating body node 109, and lowering the threshold voltage (VT) of cell 100. Conversely, a logic xe2x80x9c0xe2x80x9d data bit is written into DRAM cell 100 by biasing drain node 106 to a negative voltage while gate node 111 is biased at a mid-level voltage, thereby forward biasing the floating body-to-drain junction and removing holes from floating body 109, thereby raising the threshold voltage (VT) of cell 100.
A read operation is performed by applying mid-level voltages to both drain node 106 and gate node 111 (while source node 105 remains grounded). Under these conditions, a relatively large drain-to-source current will flow if DRAM cell 100 stores a logic xe2x80x9c1xe2x80x9d data bit, and a relatively small drain-to source current will flow if DRAM cell 100 stores a logic xe2x80x9c0xe2x80x9d data bit. The level of the drain-to-source current is compared with the current through a reference cell to determine the difference between a logic xe2x80x9c0xe2x80x9d and a logic xe2x80x9c1xe2x80x9d data bit. Non-selected DRAM cells in the same array as DRAM cell 100 have their gate nodes biased to a negative voltage to minimize leakage currents and disturbances from read and write operations.
One significant disadvantage of conventional 1T/FB DRAM cell 100 is that it requires the use of partially depleted silicon-on-insulator (PD-SOI) process, which is relatively expensive and not widely available. In addition, the floating body effect of the SOI process, although utilized in the 1T/FB DRAM cell advantageously, complicates circuit and logic designs significantly and often requires costly substrate connections to eliminate undesired floating body nodes not located in the 1T/FB DRAM cells. Further, with a PD-SOI process, the device leakage characteristics can be difficult to control due to the lack of effective backgate control of the bottom interface of the silicon layer that includes silicon regions 107-109.
Conventional 1T/FB DRAM cells are described in more detail in xe2x80x9cA Capacitor-less 1T-DRAM Cell,xe2x80x9d S. Okhonin et al, pp.85-87, IEEE Electron Device Letters, Vol. 23, No.2, February 2002, and xe2x80x9cMemory Design Using One-Transistor Gain Cell on SOI,xe2x80x9d T. Ohsawa et al, pp.152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002.
Therefore, one object of the present invention is to provide a 1T/FB DRAM cell that is compatible with a conventional bulk CMOS process, and is compatible with conventional logic processes and conventional logic designs.
It is another object of the present invention to provide a vertical transistor having a gate electrode located at least partially inside a recessed region formed in a shallow-trench isolation (STI) region, wherein the charge storage body region of the vertical transistor is fully isolated.
Accordingly, the present invention provides a one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell that includes a vertical field-effect transistor fabricated in a semiconductor substrate using a process compatible with a bulk CMOS process.
The 1T/FB DRAM cell of the present invention is fabricated in a semiconductor substrate having an upper surface. A shallow trench isolation (STI) region is located in the semiconductor substrate, wherein the STI region defines a semiconductor island region in the semiconductor substrate. The STI region extends a first depth below the upper surface of the semiconductor substrate. A recessed region located in the STI region exposes a sidewall region of the semiconductor island region. This sidewall region can include one or more sidewalls of the semiconductor island region. The recessed region (and therefore the sidewall region) extends a second depth below the upper surface of the semiconductor substrate, wherein the second depth is less than the first depth (i.e., the recessed region does not extend to the bottom of the STI region).
A gate dielectric layer is located on the sidewall region of the semiconductor island region. A gate electrode is located in the recessed region, and contacts the gate dielectric layer. In one embodiment, a portion of the gate electrode extends over the upper surface of the semiconductor substrate.
A buried source region is located in the semiconductor substrate, wherein the buried source region has a top interface located above the second depth, and a bottom interface located below the first depth. A drain region is located in the semiconductor island region at the upper surface of the semiconductor substrate. A floating body region is located in the semiconductor island region between the drain region and the buried source region. A dielectric spacer can be formed adjacent to the gate electrode and over exposed edges of the gate dielectric layer, thereby preventing undesirable current leakage and shorting.
If the vertical transistor is an NMOS transistor, a logic xe2x80x9c1xe2x80x9d data bit is written to the 1T/FB DRAM cell using a hot carrier injection mechanism, and a logic xe2x80x9c0xe2x80x9d data bit is written to the 1T/FB DRAM cell using a junction forward bias mechanism.
The present invention also includes a method of fabricating the 1T/FB DRAM cell. This method includes forming a shallow trench isolation (STI) region having a first depth in a semiconductor substrate, wherein the STI region defines a semiconductor island region in the semiconductor substrate. A buried source region having a first conductivity type is then formed below the upper surface of the semiconductor substrate. The buried source region is formed such that a top interface of the buried source region is located above the first depth, and a bottom interface of the buried source region is located below the first depth. In one embodiment, the buried source region is formed by an ion implantation step.
A recessed region is etched in the STI region adjacent to the semiconductor island region, wherein the recessed region extends a second depth below the upper surface of the substrate. The second depth is less than the first depth (i.e., the recessed region does not extend to the bottom of the STI region). The step of etching the recessed region exposes one or more sidewalls of the semiconductor island region. The top interface of the buried source region is located above the second depth, thereby enabling the formation of a vertical transistor along the sidewalls of the recessed region.
A gate dielectric layer is formed over the sidewalls of the semiconductor island region exposed by the recessed region. A gate electrode is then formed in the recessed region, wherein the gate electrode contacts the gate dielectric layer. A portion of the gate electrode extends over the upper surface of the semiconductor substrate. A drain region of the first conductivity type is formed in the semiconductor island region, wherein the drain region is continuous with the upper surface of the semiconductor substrate. The formation of the buried source region and the drain region result in the formation of a floating body region of the second conductivity type between the drain region and the buried source region in the semiconductor island region. A dielectric spacer can be formed adjacent to the gate electrode, wherein the dielectric spacer extends over an edge of the gate dielectric layer at the upper surface of the semiconductor substrate.
The method can also include forming a well region having the first conductivity type in the semiconductor substrate, wherein the buried source region contacts the well region. Alternately, the method can include forming a deep well region having the first conductivity type in the semiconductor substrate, wherein the deep well region is located below and continuous with the buried source region.
The present invention will be more fully understood in view of the following description and drawings.